1. Field of the Invention
This invention relates generally to fabrication of integrated circuits, and more particularly to controlling the channel length of transistors by laterally diffusing a nitrogen implant.
2. Description of the Related Art
MOSFETs (metal-oxide-semiconductor-field-effect transistors) are the basic building blocks of modern integrated circuits. The conventional fabrication of MOSFET devices is well known. Typically, MOSFETs are manufactured by depositing an undoped polycrystalline silicon (xe2x80x9cpolysiliconxe2x80x9d) material over a relatively thin gate oxide arranged above a semiconductor substrate. The polysilicon material and the gate oxide are patterned to form a gate conductor arranged between a source region and a drain region. The gate conductor and source/drain regions are then implanted with an impurity dopant. If the dopant species employed for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET (n-channel) transistor device. Conversely, if the source/drain dopant species is p-type, then the resulting MOSFET is a PMOSFET (p-channel) transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single monolithic substrate.
The dimensions of MOSFETs play a critical role in determining the speed and complexity of integrated circuits. The complexity of an integrated circuit is a function of the number of MOSFETs that can be packed into a given substrate area. Clearly, reducing the lateral width of the gate conductor will translate into an increased transistor surface density. Decreasing the width of the gate conductor, and hence the channel length also reduces the transistor threshold voltage, VT, which in turn leads to faster integrated circuits. Several factors contribute to VT, one of which is the effective channel length (xe2x80x9cLeffxe2x80x9d) of the transistor. The initial distance between the source and the drain of a transistor is often referred to as the physical channel length. However, after implantation and subsequent diffusion of the source/drain regions, the actual distance between the source and drain becomes less than the physical channel length and is often referred to as the effective channel length, Leff. In VLSI designs, as the physical channel length decreases, so too must Leff Decreasing Leff reduces the distance between the depletion regions associated with the source and drain of a transistor. As a result, less gate charge is required to invert the channel of a transistor having a shorter Leff. Accordingly, reducing the physical channel length, and hence the Leff, can lead to a reduction in the threshold voltage of a transistor. Consequently, the switching speed of the logic gates of an integrated circuit employing transistors with reduced Leff is faster, allowing the integrated circuit to quickly transition between logic states (i.e., operate at high frequencies).
Minimization of the physical channel length of a transistor is limited by conventional techniques used to define the gate conductor of the transistor. As transistor geometries shrink below 0.5 micron, the limitations of conventional transistor processing become more and more apparent. As previously indicated, gate conductors are typically formed from polysilicon. A technique known as optical lithography, or photolithography, is used to pattern a photosensitive film (i.e., photoresist) formed above the polysilicon material. According to this technique, an optical image is transferred to the photoresist by projecting electromagnetic radiation, typically ultraviolet light, through the transparent portions of a mask plate. The solubility of photoresist regions exposed to the radiation is altered by a photochemical reaction. The photoresist is washed with a solvent that preferentially removes the altered resist areas of higher solubility. Exposed portions of the polysilicon material not protected by photoresist are etched away, defining the geometric shape of a polysilicon gate conductor.
The lateral width (i.e., the distance between opposed sidewall surfaces) of the gate conductor, which dictates the physical channel length of a transistor, is thus defined by the lateral width of an overlying photoresist layer. The minimum lateral dimension that can be achieved for a patterned photoresist layer is unfortunately limited by the resolution of the optical system (i.e., aligner or printer) used to project the image onto the photoresist. The term xe2x80x9cresolutionxe2x80x9d describes the ability of an optical system to distinguish closely spaced objects.
Resolution in photolithography systems is limited by diffraction effects, which spread radiation from the illumination source into regions of the photoresist which are not directly exposed to the illumination source. Because of diffraction effects, there is a minimum distance beyond which even a geometrically perfect lens cannot resolve two points. In other words, when two points are less than a minimum distance from each other, the two points cannot be resolved by the lithography system. The diffraction patterns associated with each point overlap each other to such an extent that the two points cannot be effectively differentiated. The resolution of a lens depends on the wavelength of the illumination source and the numerical aperture of the lens. Rayleigh""s criteria defines two images as being resolvable when the intensity between them drops to 80% of the image intensity. This criteria is satisfied when 2d=0.61xcex/NA, where 2d is the distance separating two images, xcex is the wavelength of the radiation, and NA is the numerical aperture of the lens. Thus, for a given photolithography system, Rayleigh""s criteria predicts a threshold. Beyond this photolithography threshold, the features patterned upon a masking plate may be skewed, enlarged, shortened, or otherwise incorrectly printed onto the photoresist.
It would be advantageous to develop a technique for manufacturing a transistor in which the channel length of the transistor is reduced to provide for high-frequency operation of an integrated circuit employing the transistor. More specifically, a process is needed in which the lateral width of the gate conductor and underlying channel length are no longer dictated by the resolution of photolithography systems.
The problems outlined above are overcome by laterally diffusing a nitrogen implant to shrink the channel length of a transistor below the photolithography threshold. Controlled diffusion of nitrogen implanted into select regions of a gate conductor layer can be used to adjust the thickness of a gate conductor formed from that layer, thereby reducing the lateral dimension of the underlying channel length. Because the diffusion parameters for impurities in silicon and polysilicon can be readily calculated, it is possible to accurately control the amount of diffusion to tailor channel lengths.
According to one embodiment, a method is presented for fabricating a transistor by defining an ultra-short channel length in an active region of a semiconductor substrate. The ultra-short channel length is brought about by laterally diffusing a nitrogen implant in select regions of a gate conductor layer formed over the active region. More specifically, a semiconductor substrate is provided. The semiconductor substrate is preferably single crystal silicon lightly doped with p-type or n-type dopant species. One or more layers of gate dielectric can be formed over the semiconductor substrate. In one embodiment, a single gate oxide layer is preferably formed over the semiconductor substrate. The gate oxide layer may be thermally grown or deposited. A gate conductor layer is then formed over the gate oxide layer. Polycrystalline silicon is a suitable material for the gate conductor layer. The upper surface of the gate conductor layer includes a future gate conductor area laterally bounded by a spaced pair of target areas. Photoresist is then deposited over the gate conductor layer. The photoresist is patterned to expose the spaced pair of target areas on the upper surface of the gate conductor layer leaving only the future gate conductor area covered by photoresist.
After patterning the photoresist, nitrogen is implanted into the spaced pair of target areas to form a spaced pair of nitrogen bearing regions within the gate conductor layer. The formation of the nitrogen bearing regions is suitably accomplished by implanting a nitrogen containing molecule such as N, N2, NO, NF3, N2O, NH3, or any other molecular species containing nitrogen. A shallow implant is sufficient to accomplish the objectives contemplated herein. Ideally the distribution of nitrogen within the nitrogen bearing regions has a peak concentration preferably in the range of approximately 1xc3x971013 to 1xc3x971019 atoms/cm3, and more preferably in the range of approximately 1xc3x971015 to 1xc3x971019 atoms/cm3. The lateral distance between the spaced pair of nitrogen bearing regions defines a first width of the intervening nitrogen free region in the gate conductor layer. This first width is determined by the patterning of the photoresist. The nitrogen free region is formed under the future gate conductor area. The gate conductor will eventually be formed from this nitrogen free region. Following the nitrogen implantation and the removal of the remaining photoresist, the entire semiconductor topography is heated, preferably with a rapid anneal cycle, to laterally diffuse the nitrogen implants. The anneal causes the nitrogen in the nitrogen bearing regions to partially diffuse into the nitrogen free region resulting in a spaced pair of nitrogen diffused regions. The lateral distance between the spaced pair of nitrogen diffused regions defines a second width of the nitrogen free region less than the first width. Thus, where the first width is set at the minimum resolvable photolithography limit, lateral diffusion of the nitrogen implants necessitates that the second width will fall below the photolithography threshold. The anneal is preferably a rapid thermal process, carried out at a temperature of approximately 900 to 1100xc2x0 C. for a duration of less than approximately 5 minutes. The precise temperature and anneal time vary depending on the desired channel length. Diffusion characteristics of nitrogen in polysilicon are well known making it possible to calculate a temperature and anneal duration to achieve a specific gate conductor width and underlying channel length.
The spaced pair of nitrogen diffused regions are removed along with any underlying nitrogen free portions of the gate conductor layer to form a nitrogen free gate conductor having a channel length equal to the second width. In a preferred embodiment, an oxide mask is used to align an etch of the exposed regions of the gate conductor layer. Formation of the oxide mask entails thermally oxidizing the gate conductor layer to grow a variable thickness oxide layer over the upper surface of the gate conductor layer. The thermal oxidation can be carried out in a dry or wet oxygen ambient. Because nitrogen drastically slows oxide growth, a first oxide thickness will grow over the spaced pair of diffused nitrogen regions and a second oxide thickness will grow over the nitrogen free region, wherein the second thickness is greater than the first thickness. The oxide mask is then formed by anisotropically etching the oxide layer to expose the upper surface of the spaced pair of diffused nitrogen regions, thereby leaving a remaining oxide layer only over the nitrogen free region. Using the remaining oxide layer as the oxide mask, the exposed portions of the gate conductor layer can be etched away to leave a gate conductor having a channel length equal to the second width.
In an alternative embodiment, the annealing step and the thermal oxidation step can be combined by performing anneal in an oxygen containing ambient. Combination of the anneal and thermal oxidation is possible because nitrogen diffuses faster in polysilicon than the polysilicon oxidizes. The additional diffusion of the nitrogen implant due to thermal oxidation can be readily accounted for in precisely calculating the ultimate gate conductor width and underlying channel length.